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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
SUMMARY 300 MHz High-Performance Blackfin DSP Core Two 16-Bit MACs Two 32-Bit ALUs or Four 8-Bit Video ALUs Dual 40-Bit Accumulators 40-Bit Shifter RISC-Like Register and Instruction Model for Ease of Programming and Compiler-Friendly Support Advanced Debug, Trace, and PerformanceMonitoring Support Memory 4G-Byte Unified Address Range Two 32-Bit DAGs for General Addressing and Circular Buffer Support
ADSP-21535
308K Bytes of On-Chip Memory: 16K Bytes of Instruction SRAM/Cache 32K Bytes of Data SRAM/Cache 4K Bytes of Scratchpad SRAM 256K Bytes of Full Speed, Low Latency SRAM Memory DMA Controller Memory Management Unit Providing Memory Protection Synchronous External Memory Controller with Glueless SDRAM Support Asynchronous External Memory Controller with Glueless Support for SRAM, FLASH, ROM Flexible Memory Booting Options From SPI and External Memory
JTAG TEST AND EMULATION
INTERRUPT CONTROLLER/ TIMER
WATCHDOG TIMER
32 BLACKFIN CORE 256K BYTES SRAM REAL TIME CLOCK UART PORT 0 IrDA(R) UART PORT 1 64 SYSTEM BUS INTERFACE UNIT 32 TIMER0, TIMER1, TIMER2 GPIO 32 DMA CONTROLLER USB INTERFACE SERIAL PORTS (2) SPI PORTS (2)
BOOT ROM
32
PCI BUS INTERFACE
32
EXTERNAL PORT FLASH SDRAM CONTROL
Figure 1. ADSP-21535 Block Diagram
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. One Technology Way, P .O.Box 9106, Norwood, MA 02062-9106, U.S.A. Tel:781/329-4700 World Wide Web Site: http://www.analog.com Fax:781/326-8703 (c)Analog Devices,Inc., 2001
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PERIPHERALS 32-Bit, 33-MHz, PCI 2.2-compliant Bus Interface with Master and Slave Support Integrated USB 1.1-compliant Device Interface Event Controller Two UARTs, One with Support for IrDA(R) Three Timer/counters with PWM Support Two SPI-compatible Ports Two 6-pin Full-Duplex Synchronous Serial Ports Real-Time Clock Watchdog Timer 16 General Purpose I/O Pins Debug/JTAG Interface On Chip PLL Capable of 1x To 31x Frequency Multiplication 0.9 V to 1.5 V Core VDD with Dynamic Power Management 3.3 V-Tolerant I/O 0 C To 85 C Case Temperature Range 256-Lead PBGA Package
solutions quickly without the need for costly external components. The ADSP-21535 system peripherals include UARTs, SPIs, SPORTs, General Purpose Timers, a Real-Time Clock, Watchdog Timer, and USB and PCI buses for glueless peripheral expansion.
ADSP-21535 Peripherals
GENERAL NOTE This data sheet provides preliminary information for the ADSP-21535 Blackfin DSP.
GENERAL DESCRIPTION
The ADSP-21535 is a member of the Blackfin DSP family of products, incorporating ADI's Blackfin DSP core architecture. The Blackfin DSP architecture combines a dual-MAC state-of-the art DSP engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction set architecture. By integrating a rich set of industry leading system peripherals and memory, Blackfin DSPs are the platform of choice for next generation applications that require RISC like programmability, multimedia support and leading edge signal processing in one integrated DSP.
Portable Low-Power Architecture
The ADSP-21535 contains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance. See Figure 1 on page 1. The base peripherals include general purpose functions such as UARTs, Timers with PWM (Pulse Width Modulator) and pulse measurement capability, general purpose flag I/O pins, a Real-Time Clock, and a Watchdog Timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. In addition to these general purpose peripherals, the ADSP-21535 contains high speed serial ports for interfaces to a variety of audio and modem CODEC functions, an interrupt controller for flexible management of interrupts from the on-chip peripherals as well as external sources and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. The on-chip peripherals can be easily augmented in many system designs with little or no glue logic due to the inclusion of several interfaces providing expansion on industry-standard buses. These include a 32-bit, 33-MHz, V2.2-compliant PCI bus, SPI serial expansion ports and a device type USB port. These enable the connection of a large variety of peripheral devices to tailor the system design to specific applications with a minimum of design complexity. All of the peripherals are supported by a flexible DMA structure with individual DMA channels integrated into the peripherals as appropriate to their needs. There is also a separate memory DMA channel dedicated to data transfers between the DSP's various memory spaces including external SDRAM and asynchronous memory, internal Level 2 SRAM and PCI memory spaces. Multiple on-chip 32-bit buses running at up to 133 MHz provide adequate bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.
Blackfin DSP Core Architecture
Blackfin DSPs provide world class power consumption and performance compared to other Digital Signal Processors. Blackfin DSPs are designed in a Low-Power and Low-Voltage Design Methodology and feature Dynamic Power Management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a three-fold reduction in power consumption, by comparison to just varying the frequency of operation. This translates into longer battery life for portable appliances.
System Integration
The ADSP-21535 is a highly integrated system-on-a-chip solution for the next generation of digital communication and portable Internet appliances. By combining industry-standard interfaces with a high performance Digital Signal Processing core, users can develop cost effective
As shown in Figure 2 on page 3, the Blackfin DSP core contains two multiplier/accumulators (MACs), two 32-bit ALUs, four video ALUs, and a single shifter. The computational units process 8-bit, 16-bit, or 32-bit data from the register file. Each MAC performs a 16-bit by 16-bit multiply in every cycle, with an accumulation to a 40-bit result, providing 8 bits of extended precision.
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The ALUs perform a standard set of arithmetic and logical operations. With two ALUs capable of operating on 16- or 32-bit data, the flexibility of the computation units covers the signal processing requirements of a varied set of application needs. Each of the two 32-bit input registers can be regarded as two 16-bit halves, so each ALU can accomplish
very flexible single 16-bit arithmetic operations. By viewing the registers as pairs of 16-bit operands, dual 16-bit or single 32-bit operations can be accomplished in a single cycle. By further taking advantage of the second ALU, quad 16-bit operations can be accomplished simply, accelerating the per cycle throughput.
ADDRESS ARITHMETIC UNIT
SP FP P5 P4 P3 P2 P1 P0
I3 I2 I1 I0
L3 L2 L1 L0
B3 B2 B1 B0
M3 M2 M1 M0
DAG0
DAG1
SEQUENCER
ALIGN
DECODE R7 R6 R5 R4 R3 R2 R1 R0 8
LOOP BUFFER 16 8 8 16 8 CONTROL UNIT
BARREL SHIFTER
40 ACC 0
40 ACC 1
DATA ARITHMETIC UNIT
Figure 2. Blackfin DSP Core Architecture
The powerful 40-bit shifter has extensive capabilities for performing shifting, rotating, normalization, extraction, and depositing of data. The data for the computational units is found in a multi-ported register file of sixteen 16-bit entries or eight 32-bit entries. A powerful program sequencer controls the flow of instruction execution, including instruction alignment and decoding. The sequencer supports conditional jumps and subroutine calls, as well as zero-overhead looping. A loop buffer stores instructions locally, eliminating instruction memory accesses for tight looped code. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from memory. The DAGs share a register file containing four sets of 32-bit Index, Modify, Length, and Base registers. Eight additional 32-bit registers provide pointers for general indexing of variables and stack locations. REV. PrA
Blackfin DSPs support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. Level 2 (L2) memories are other memories on-chip or off-chip, that may take multiple processor cycles to access. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. At the L2 level, there is a single unified memory space, holding both instructions and data. In addition, the L1 instruction memory and L1 data memories may be configured as either Static RAMs (SRAMs) or caches. The Memory Management Unit (MMU) provides memory protection for individual tasks that may be operating on the core and may protect system registers from unintended access.
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The architecture provides two modes of operation, user mode and supervisor mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin DSP instruction set has been optimized so that 16-bit op-codes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit op-codes, representing fully featured multifunction instructions. Blackfin DSPs support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin DSP assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C-compiler, resulting in fast and efficient software implementations.
Memory Architecture
0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCH SRAM (4K BYTE) 0xFFB0 0000 RESERVED 0xFFA0 4000 CODE SRAM (16K BYTE) 0xFFA0 0000 RESERVED 0xFF90 4000 DATA BANK B SRAM (16K BYTE) 0xFF90 0000 RESERVED 0xFF80 4000 DATA BANK A SRAM (16K BYTE) 0xFF80 0000 RESERVED 0xF003 FFFF L2 SRAM MEMORY (256K BYTE) 0xF000 0000 RESERVED 0xEF00 0000 PCI CONFIG SPACE PORT (4 BYTE) 0xEEFF FFFC PCI CONFIG REGISTERS (64K BYTE) 0xEEFF FF00 RESERVED 0xEEFE FFFF PCI IO SPACE (64K BYTE) RESERVED 0xE7FF FFFF PCI MEMORY SPACE (128M BYTE) 0xE000 0000 RESERVED 0x2FFF FFFF ASYNC MEMORY BANK 3 (64M BYTE) 0x2C00 0000 ASYNC MEMORY BANK 2 (64M BYTE) 0x2800 0000 ASYNC MEMORY BANK 1 (64M BYTE) 0x2400 0000 ASYNC MEMORY BANK 0 (64M BYTE) 0x2000 0000 0x1800 0000 0x1000 0000 0x0800 0000 0x0000 0000 SDRAM MEMORY BANK 3 (16 MB - 128 MB)* SDRAM MEMORY BANK 2 (16 MB - 128 MB)* SDRAM MEMORY BANK 1 (16 MB - 128 MB)* SDRAM MEMORY BANK 0 (16 MB - 128 MB)* 0xEEFE 0000
The L1 memory system is the primary highest-performance memory available to the Blackfin DSP core. The L2 memory provides much more capacity; however, read latency is higher. Lastly, the off-chip memory system, accessed through the External Memory Controller (EMC), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing more than 768M bytes of physical memory. The memory DMA controller provides high-bandwidth, multi-channel, data-movement capability. It can perform block transfers of code or data between the internal L1/L2 memories and the external memory spaces (including PCI memory space).
Internal (On-chip) Memory
*THE ADDRESSES SHOWN FOR THE SDRAM BANKS REFLECT A FULLY POPULATED SDRAM ARRAY WITH 512M BYTE OF MEMORY. IF ANY OF THE BANKS CONTAIN LESS THAN 128M BYTE OF MEMORY, IT WOULD EXTEND ONLY TO THE LENGTH OF THE REAL MEMORY SYSTEMS AND THE END ADDRESS WOULD BECOME THE START ADDRESS OF THE NEXT BANK. THIS WOULD CONTINUE FOR ALL FOUR BANKS WITH ANY REMAINING SPACE BETWEEN THE END OF MEMORY BANK 3 AND THE BEGINNING OF ASYNC MEMORY BANK 0 AT ADDRESS 0x2000 0000 TREATED AS RESERVED ADDRESS SPACE.
The ADSP-21535 has four blocks of on-chip memory providing high-bandwidth access to the core. The first is the L1 instruction memory consisting of 16K bytes of 4-way set-associative cache memory. In addition the memory may be configured as an SRAM. This memory is accessed at full processor speed.
Figure 3. ADSP-21535 Internal/External Memory Map
The second on-chip memory block is the L1 data memory, consisting of two blocks of 16K bytes each. Each L1 data memory may be configured as a set-associative cache or as an SRAM, and is accessed at full speed by the core.
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EXTERNAL MEMORY MAP
The ADSP-21535 views memory as a single unified 4G-byte address space, using 32-bit addresses. All resources including internal memory, external memory, PCI address spaces, and I/O control registers occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency memory as cache or SRAM very close to the processor, and larger, lower-cost and performance-memory systems farther away from the processor. See Figure 3.
INTERNAL MEMORY MAP
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The third memory block is a 4K-byte scratchpad RAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory. The fourth on-chip memory system is the L2 SRAM memory array which provides 256 KBytes of high speed SRAM at the full bandwidth of the core, and slightly longer latency than the L1 memory blocks. The L2 memory is a unified instruction and data memory and can hold any mixture of code and data required by the system design. The Blackfin DSP core has a dedicated low-latency 64-bit wide datapath port into the L2 SRAM memory. For example, at a core frequency of 300 MHz, the peak data transfer rate across this interface is in excess of 2.4G bytes per second.
External (Off-Chip) Memory
The PCI memory region is a 4G-byte space that appears on the PCI bus and can be used to map memory I/O devices on the bus. The ADSP-21535 uses a 128M-byte window in memory space to see a portion of the PCI memory space. A base address register is provided to position this window anywhere in the 4 gigabyte PCI memory space while its position with respect to the processor addresses remains fixed. The PCI I/O region is also a 4G-byte space. However, most systems and I/O devices only use a 64K-byte subset of this space for I/O mapped addresses. The ADSP-21535 implements a 64K-byte window into this space along with a base address register which can be used to position it anywhere in the PCI I/O address space, while the window remains at the same address in the processor's address space. PCI configuration space is a limited address space, which is used for system enumeration and initialization and which is a very low-performance communication mode between the processor and PCI devices. The ADSP-21535 provides a one-value window to access a single data value at any address in PCI configuration space. This window is fixed and receives the address of the value, and the value if the operation is a write. Otherwise the device returns the value into the same address on a read operation.
I/O Memory Space
External memory is accessed via the External Memory Controller. This interface provides a glueless connection to up to four banks of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The PC133-compliant SDRAM controller can be programmed to interface to up to four banks of SDRAM, with each bank containing between 16M bytes and 128M bytes providing access to up to 512M bytes of SDRAM. Each bank is independently programmable and is contiguous with adjacent banks regardless of the sizes of the different banks or their placement. This allows flexible configuration and upgradability of system memory while allowing the core to view all RAM as a single, contiguous, physical address space. The asynchronous memory controller can also be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 64M-byte segment regardless of the size of the devices used so that these banks will only be contiguous if fully populated with 64M bytes of memory.
PCI
The PCI bus defines three separate address spaces, which are accessed through windows in the ADSP-21535 memory space. These are PCI memory, PCI I/O, and PCI configuration space. In addition, the PCI interface can either be used as a bridge from the processor core as the controlling CPU in the system, or as a host port where another CPU in the system is the host and the ADSP-21535 is functioning as an intelligent I/O device on the PCI bus. When the ADSP-21535 acts as the system controller, it views the PCI address spaces through its mapped windows and can initialize all devices in the system and maintain a map of the topology of the environment. REV. PrA
Blackfin DSPs do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G-byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all CPU core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the CPU core. The core MMRs are accessible only by the core and only in supervisor mode and appear as reserved space by on-chip peripherals, as as well as external devices accessing resources through the PCI bus. The system MMRs are accessible by the core in supervisor mode and can be mapped as either visible or reserved to other devices, depending on the system protection model desired.
Boot Memory Space
The internal boot ROM contains a small boot kernel, which configures the appropriate peripheral for booting. If the ADSP-21535 is configured to boot from boot ROM memory space, the DSP starts executing from the on-chip boot ROM. For more information, see "Booting Modes" on page 15.
Event Handling
The event controller on the ADSP-21535 handles all asynchronous and synchronous events to the processor. The ADSP-21535 provides event handling that supports both 5
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EVT Entry
nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The controller provides support for five different types of events: * Emulation - An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. Reset - This event resets the processor. Non-Maskable Interrupt (NMI) - The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to allow an orderly shut down of the system. Exceptions - Exceptions are events that occur synchronously to program flow, i.e., the exception will be taken before the instruction is allowed to complete. Conditions such as data alignment violations, undefined instructions, etc. cause exceptions. Interrupts - Interrupts are events that occur asynchronously to program flow. They are caused by timers, peripherals, input pins, etc.
Table 1. Core Interrupt Controller (CIC) Priority (0 is Highest) Event Class
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Emulation/Test Control Reset Non-Maskable Interrupt Exceptions Global Interrupt Enable Hardware Error Core Timer General Interrupt 7 General Interrupt 8 General Interrupt 9 General Interrupt 10 General Interrupt 11 General Interrupt 12 General Interrupt 13 General Interrupt 14 General Interrupt 15
EMUN IRST NMI EVSW IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
* *
*
*
Each event has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the kernel stack. The ADSP-21535 event controller consists of two stages, the Core Interrupt Controller (CIC) and the System Interrupt Controller (SIC). The Core Interrupt Controller works with the System Interrupt Controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CIC.
Core Interrupt Controller (CIC)
Table 2. System Interrupt Controller (SIC) Peripheral Interrupt Event Peripheral Interrupt ID Default Mapping
The CIC supports nine general-purpose interrupts (IVG7:15), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority interrupts (IVG14:15) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-21535. Table 1 describes the inputs to the CIC, identifies their names in the Event Vector Table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
Real-Time Clock Interrupt Reserved USB Interrupt PCI Interrupt SPORT 0 RCV DMA Interrupt SPORT 0 XMT DMA Interrupt SPORT 1 RCV DMA Interrupt
0 1 2 3 4 5 6
IVG7 IVG7 IVG7 IVG8 IVG8 IVG8
The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources, to the prioritized general-purpose interrupt inputs of the CIC. Although the ADSP-21535 provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the Interrupt Assignment Registers (IAR). Table 2 describes the inputs into the ECIC and the default mappings into the 6
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Peripheral Interrupt Event
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Table 2. System Interrupt Controller (SIC) (Continued) Peripheral Interrupt ID Default Mapping
SPORT 1 XMT DMA Interrupt SPI 0 DMA Interrupt SPI 1 DMA Interrupt UART 0 RCV Interrupt UART 0 XMT Interrupt UART 1 RCV Interrupt UART 1 XMT Interrupt Timer A Interrupt Timer B Interrupt Timer C Interrupt GPIO Interrupt A GPIO Interrupt B Memory DMA Interrupt Software Watchdog Timer Interrupt Reserved Software Interrupt 1 Software Interrupt 2
Event Control
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21:26 27 28
IVG8 * IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG12 IVG12 IVG13 IVG13 IVG14 IVG15 * *
servicing the event even though the event may be latched in the ILAT register. This register may be read from or written to while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) CIC Interrupt Pending Register (IPEND) - The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 2 on page 6. * SIC Interrupt Mask Register - This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in the register, that peripheral event is unmasked and will be processed by the system when asserted. A cleared bit in the register masks the peripheral event thereby preventing the processor from servicing the event. SIC Interrupt Status Register - As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, a cleared bit indicates the peripheral is not asserting the event. SIC Interrupt Wakeup Enable Register - By enabling the corresponding bit in this register, each peripheral can be configured to wake up the processor, should the processor be in a powered down mode when the event is generated. (For more information, see "Low-Power Operation" on page 12.)
The ADSP-21535 provides the user with a very flexible mechanism to control the processing of events. In the CIC, three registers are used to coordinate and control events. Each register is 16-bits wide, while each bit represents a particular event class: * CIC Interrupt Latch Register (ILAT) - The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller but may be read while in supervisor mode. CIC Interrupt Mask Register (IMASK) - The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the system when asserted. A cleared bit in the IMASK register masks the event thereby preventing the processor from
Because multiple interrupt sources can map to a single general-purpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two processor clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CIC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the general-purpose interrupt to the IPEND output asserted is three processor clock cycles; however, the latency can be much higher, depending on the activity within and the mode of the processor.
*
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DMA Controller
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The ADSP-21535 has a DMA controller that supports automated data transfers with minimal overhead for the DSP core. Cycle stealing DMA transfers can occur between the ADSP-21535's internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller, the asynchronous memory controller and the PCI bus interface. DMA-capable peripherals include the SPORTs, SPI ports, UARTs, and USB port. Each individual DMA-capable peripheral has a dedicated DMA channel. DMA to and from PCI is accomplished by the memory DMA channel. To describe each DMA sequence, the DMA controller uses a set of parameters, called a transfer control block (TCB). When successive DMA sequences are needed, these TCBs can be linked or chained together, so the completion of one DMA sequence auto-initiates and starts the next sequence. The TCBs include full 32-bit addresses for the base pointers for source and destination enabling access to the entire ADSP-21535 address space. In addition to the dedicated peripheral DMA channels, there is a separate memory DMA channel provided for transfers between the various memories of the ADSP21535 system. This enables transfers of blocks of data between any of the memories including on-chip Level 2 memory, external SDRAM, ROM, SRAM and flash memory, and PCI address spaces with little processor intervention.
External Memory Controller
A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. The memory banks can be configured as either 32-bits wide for maximum performance and bandwidth or 16-bits wide for minimum device count and lower system cost. All four banks share common SDRAM control signals and have their own bank select lines providing a completely glueless interface for most system configurations.
Asynchronous Controller
The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety of memory devices including SRAM, ROM, and flash EPROM, as well as I/O devices that interface with standard memory control lines. Each bank occupies a 64M-byte window in the processor's address space but, if not fully populated, these are not made contiguous by the memory controller logic. The banks can also be configured as 16-bit wide or 32-bit wide buses for ease of interfacing to a range of memories and I/O devices tailored either to high performance or to low cost and power.
PCI Interface
The ADSP-21535 provides a glueless logical and electrical, 33-Mhz, 32-bit PCI (Peripheral Component Interconnect), Revision 2.2-compliant interface. The PCI interface provides a bus bridge function between the processor core and on-chip peripherals and an external PCI bus. The PCI interface of the ADSP-21535 supports two PCI functions: * A Host to PCI Bridge function, in which the ADSP-21535 resources (the processor core, internal and external memory, and the memory DMA controller) provide the necessary hardware components to emulate a host PC PCI interface, from the perspective of a PCI target device. A PCI Target function, in which an ADSP-21535 based intelligent peripheral can be designed to easily interface to a Revision 2.2-compliant PCI bus.
The external memory controller on the ADSP-21535 provides a high performance, glueless interface to a wide variety of industry-standard memory devices. The controller is made up of two sections: the first is an SDRAM controller for connection of industry-standard synchronous DRAM devices and DIMMs, while the second is an asynchronous memory controller intended to interface to a variety of memory devices.
PC133 SDRAM Controller
*
The SDRAM controller provides an interface to up to four separate banks of industry-standard SDRAM devices or DIMMs, at speeds up to fSCLK. Fully compliant with the PC133 SDRAM standard, each bank can be configured to contain between 16M bytes and 128M bytes of memory. The controller maintains all of the banks as a contiguous address space so that the processor sees this as a single address space, even if different size devices are used in the different banks. This enables system designs that are delivered with an initial configuration that can be upgraded at a future time with either similar or different memories.
PCI Host Function
As the PCI host, the ADSP-21535 provides the necessary PCI host (platform) functions required to support and control a variety of off-the-shelf PCI I/O devices (e.g., Ethernet controllers, bus bridges, etc.) in a system in which the ADSP-21535 processor is the host. Note that the Blackfin DSP architecture defines only memory space (no I/O or config address spaces). The three memory spaces of PCI space (memory, IO, and configuration space) are mapped into the flat 32-bit memory space of the ADSP-21535. Since the PCI memory space is as large as the ADSP-21535 memory address space, a segmented, or windowed, approach is employed, with separate windows REV. PrA
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in the ADSP-21535 address space used for accessing the three PCI address spaces. Base address registers are provided so that these windows can be positioned to view any range in the PCI address spaces while they remain fixed in position in the ADSP-21535 processor's address range. For devices on the PCI bus viewing the ADSP-21535's resources, several mapping registers are provided to enable resources to be viewed in the PCI address space. The ADSP-21535's external memory space, internal L2, and some I/O MMRs can be selectively enabled as memory spaces that devices on the PCI bus can use as targets for PCI memory transactions.
PCI Target Function
When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value, with one minute resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the ADSP-21535 processor from a low-power state upon generation of any interrupt.
Watchdog Timer
As a PCI target device, the PCI host processor can configure the ADSP-21535 subsystem during enumeration of the PCI bus system. Once configured, the ADSP-21535 subsystem acts as an intelligent I/O device. When configured as a target device, the PCI controller uses the memory DMA controller to perform DMA transfers as required by the PCI host.
USB Port
The ADSP-21535 provides a USB 1.1- compliant device type interface to support direct connection to a host system. The USB core interface provides a flexible programmable environment with up to eight endpoints. Each endpoint can support all of the USB data types including Control, Bulk, Interrupt, and Isochronous. Each endpoint provides a memory-mapped buffer for transferring data to the application. The ADSP-21535 USB port has a dedicated DMA controller and interrupt input to minimize processor polling overhead and to enable asynchronous requests for CPU attention only when transfer management is required.
Real-Time Clock
The ADSP-21535 includes a 32-bit timer, which can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state, via generation of a hardware reset, non-maskable interrupt (NMI), or general purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. If configured to generate a hardware reset, the timer can be programmed to reset only the ADSP-21535 CPU, or both the CPU and the ADSP-21535 peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the timer control register, which is set only upon a watchdog generated reset. The timer is clocked by the system clock (SCLK), at a maximum frequency of fSCLK.
Timers
The ADSP-21535 Real-Time Clock (RTC) provides a robust set of digital watch features, including current time, stop watch, and alarm. The RTC is clocked by a 32.768 KHz crystal external to the ADSP-21535. The RTC peripheral has dedicated power supply pins, so that it can remain powered up and clocked, even when the rest of the processor is in a low-power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. The 32.768 KHz input clock frequency is divided down to a 1Hz signal by a prescaler. The counter function of the timer consists of four counters: a 6-bit second counter, a 6-bit minute counter, a 5-bit hours counter, and an 8-bit day counter.
There are three general-purpose programmable timer units in the ADSP-21535. Each timer has one external pin that can be configured either as a Pulse Width Modulator (PWM) or timer output, as an input to clock the timer, or for measuring pulse widths of external events. Each of the three timer units can be independently programmed as a PWM, internally or externally clocked timer, or pulse width counter. The timer units can be used in conjunction with the UARTs to measure the width of the pulses in the data stream to provide an auto-BAUD detect function for a serial channel. The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the processor clock or to a count of external signals.
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In addition to the three general-purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.
Serial Ports (SPORTs)
Serial Peripheral Interface (SPI) Ports
The ADSP-21535 has two SPI-compatible ports that enable the processor to communicate with multiple SPI-compatible devices. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSIx, and Master Input-Slave Output, MISOx) and a clock pin (Serial Clock, SCKx). Two SPI chip select input pins (SPISSx) let other SPI devices select the DSP, and fourteen SPI chip select output pins (SPIxSEL7-1) let the DSP select other SPI devices. The SPI select pins are reconfigured Programmable Flag pins. Using these pins, the SPI ports provide a full duplex, synchronous serial interface, which supports both master and slave modes and multimaster environments. Each SPI port's baud rate and clock phase/polarities are programmable (see Figure 4), and each has an integrated DMA controller, configurable to support both transmit and receive data streams. The SPI's DMA controller can only service unidirectional accesses at any given time.
The ADSP-21535 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: * * Bidirectional operation - each SPORT has independent transmit and receive pins. Buffered (8-deep) transmit and receive ports - each port has a data register for transferring data words to and from other DSP components and shift registers for shifting data in and out of the data registers. Clocking - each transmit and receive port can either use an external serial clock (fSCLK) or generate its own, in frequencies ranging from (fSCLK/131070) Hz to (fSCLK/2) Hz. Word length - each SPORT supports serial data words from 3 to 16 bits in length transferred in Big Endian (MSB) or Little Endian (LSB) format. Framing - each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync. Companding in hardware - each SPORT can perform A-law or -law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. DMA operations with single-cycle overhead - each SPORT can automatically receive and transmit multiple buffers of memory data, one data word each DSP cycle. Either the DSP's core or a host processor can link or chain sequences of DMA transfers between a SPORT and memory. The chained DMA can be dynamically allocated and updated through the Transfer Control Blocks (TCBs, or DMA parameters) that set up the chain. Interrupts - each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. Multichannel capability - each SPORT supports 24 or 32 channels and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.
*
*
fSCLK HCLK SPI Clock Rate = -------------------------------------2 x SPIBAUD
Figure 4. SPI Clock Rate Calculation
*
*
During transfers, the SPI ports simultaneously transmit and receive by serially shifting data in and out on their two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines. In master mode, the DSP performs the following sequence to set up and initiate SPI transfers: 1. 2. 3. 4. Enables and configures the SPI port's operation (data size, and transfer format). Selects the target SPI slave with an SPIxSELy output pin (reconfigured Programmable Flag pin). Defines one or more TCBs in the DSP's memory space (optional in DMA mode only). Enables the SPI DMA engine and specifies transfer direction (optional in DMA mode only). a. In non-DMA mode only, reads or writes the SPI port receive or transmit data buffer.
*
*
*
The SCKx line generates the programmed clock pulses for simultaneously shifting data out on MOSIx and shifting data in on MISOx. In DMA mode only, transfers continue until the SPI DMA word count transitions from 1 to 0.
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In slave mode, the DSP performs the following sequence to set up the SPI port to receive data from a master transmitter: 1. Enables and configures the SPI slave port to match the operation parameters set up on the master (data size and transfer format) SPI transmitter. Defines and generates a receive TCB in the DSP's memory space to interrupt at the end of the data transfer (optional in DMA mode only). Enables the SPI DMA engine for a receive access (optional in DMA mode only). Starts receiving the data on the appropriate SPI SCKx edges after receiving an SPI chip select on an SPISSx input pin (reconfigured Programmable Flag pin) from a master. In DMA mode only, reception continues until the SPI DMA word count transitions from 1 to 0. The DSP can continue, by queuing up the next command TCB. A slave mode transmit operation is similar, except the DSP specifies the data buffer in memory from which to transmit data, generates and relinquishes control of the transmit TCB, and begins filling the SPI port's data buffer. If the SPI controller isn't ready on time to transmit, it can transmit a "zero" word.
UART Port
Each UART port's baud rate (see Figure 5), serial data format, error code generation and status, and interrupts are programmable: * * * Supporting bit rates ranging from (fSCLK/ 1048576) to (fSCLK/16) bits per second. Supporting data formats from 7 to 12 bits per frame. Both transmit and receive operations can be configured to generate maskable interrupts to the processor.
2.
3. 4.
fSCLK HCLK UART Clock Rate = -----------------16 x D
Figure 5. UART Clock Rate Calculation1
1
Where D = 1 to 65536
In conjunction with the general purpose timer functions, autobaud detection is supported. The capabilities of UART0 are further extended with support for the InfraRed Data Association (IrDA(R)) Serial InfraRed Physical Layer Link Specification (SIR) protocol.
Programmable Flags (PFx)
The ADSP-21535 provides two full duplex Universal Asynchronous Receiver/Transmitter (UART) ports (UART0 and UART1) fully compatible with the 16450 standard. The UART ports provide a simplified UART interface to other peripherals or hosts, supporting full duplex, DMA supported, asynchronous transfers of serial data. Each UART port includes support for 5 to 8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The UART ports support two modes of operation: * PIO (Programmed I/O) - The processor sends or receives data by writing or reading I/O-mapped UATX or UARX registers, respectively. The data is double-buffered on both transmit and receive. DMA (Direct Memory Access) - The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. Each UART has two dedicated DMA channels, one for transmit and one for recieve. These DMA channels have lower priority than most DMA channels because of their relatively low service rates.
The ADSP-21535 has 16 bi-directional, general-purpose I/O, Programmable Flag (PF0:15) pins. The Programmable Flag pins have special functions for clock multiplier selection, SROM boot mode, and SPI port operation. For more information, see "Serial Peripheral Interface (SPI) Ports" on page 10 and "Clock Signals" on page 14. Each programmable flag can be individually controlled by manipulation of the flag control, status and interrupt registers: * * Flag Direction Control Register - Specifies the direction of each individual PFx pin as input or output. Flag Control and Status Registers - Rather than forcing the software to use a read-modify-write process to control the setting of individual flags, the ADSP-21535 employs a "write one to set" and "write one to clear" mechanism that allows any combination of individual flags to be set or cleared in a single instruction, without affecting the level of any other flags. Two control registers are provided, one register is written to in order to set flag values while another register is written to in order to clear flag values. Reading the flag status register allows software to interrogate the sense of the flags. Flag Interrupt Mask Registers - The two Flag Interrupt Mask Registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the two Flag Control Registers that are used to set and clear individual flag values, one Flag Interrupt Mask Register sets bits to enable interrupt function, and the other Flag Interrupt Mask register clears bits to disable interrupt function. PFx pins defined as inputs can be 11
*
*
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configured to generate hardware interrupts, while output PFx pins can be configured to generate software interrupts. * Flag Interrupt Sensitivity Registers - The two Flag Interrupt Sensitivity Registers specify whether individual PFx pins are level- or edge-sensitive and specify-if edge-sensitive-whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.
Full On Operating Mode - No power savings
In the Full On mode, the PLL is enabled, and is not bypassed, providing the maximum operational frequency. This is the normal execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed.
Active Operating Mode - Low power savings
Low-Power Operation
The ADSP-21535 has four low-power operating modes described below that significantly reduce power consumption when the processor operates in reduced performance conditions. In addition, the extended core power management controller provides the control functions, with the appropriate external power regulation capability, to dynamically alter the processor core supply voltage, further reducing power consumption. Control of clocking to each of the ADSP-21535 peripherals also reduces power consumption. See Table 3 for a summary of the power settings for each mode.
Table 3. Power Settings Mode PLL
In the Active mode, the PLL is enabled, but bypassed. The input clock (CLKIN) is used to directly generate the clocks for the processor core (CCLK) and peripherals (SCLK). Significant power savings can be achieved with the processor running at one-half the CLKIN frequency. In this mode the PLL multiplication ratio can be changed by setting the appropriate values in the SSEL fields of the PLL control register (PLLCTL). The PLL lock counter (PLL LOCKCNT) determines when the new multiplier ratio takes effect. When in the Active mode, system DMA access to appropriately configured L1 memory is supported.
PLL Bypassed
Core Clock (CCLK)
System Clock (SCLK)
Full On Active Relaxed Sleep Deep Sleep
Enabled Enabled Disabled Disabled Disabled
No Yes - - -
Enabled Enabled Enabled Disabled Disabled
Enabled Enabled Enabled Enabled Disabled
Relaxed Operating Mode - Medium power savings
Sleep Operating Mode - High power savings
The Relaxed mode reduces power consumption by not only bypassing the PLL but also disabling it. The input clock (CLKIN) is directly used to generate the clocks for the processor core (CCLK) and peripherals (SCLK). As in the Active mode, significant dynamic power savings can be achieved with the processor running at one-half the CLKIN frequency and, unlike the Active mode, further power savings are accomplished with the PLL being disabled. In this mode the PLL multiplication ratio can be changed by setting the appropriate values in the SSEL fields of the PLL control register (PLLCTL). The PLL lock counter (PLL LOCKCNT) determines when the new multiplier ratio takes effect. When in the Relaxed mode, system DMA access to appropriately configured L1 memory is supported.
The Sleep mode reduces power consumption by disabling the clock to the processor core (CCLK). The system clock (SCLK) however, continues to operate in this mode. Any interrupt, typically via some external event or RTC activity, will wake up the processor. When in the Sleep mode, assertion of any interrupt will cause the processor to sense the value of the bypass bit (BYPASS) in the PLL control register (PLLCTL). If bypass is disabled, the processor will transition to the Full On mode. If bypass is enabled, the processor will transition to the Active mode. When in the Sleep mode, system DMA access to L1 memory is not supported.
Deep Sleep Operating Mode - Maximum power savings
The Deep Sleep mode maximizes power savings by disabling the clocks to the processor core (CCLK) and to all synchronous systems (SCLK). Asynchronous systems, such
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DEEP SL EE P
as the RTC, may still be running but will not be able to access internal resources or external memory. This powered down mode can only be exited by assertion of the reset interrupt (RESET) or by an asynchronous interrupt generated by the RTC. When in Deep Sleep mode, assertion of RESET causes the processor to sense the value of the BYPASS pin. If bypass is disabled, the processor will transition to the Full On mode. If bypass is enabled, the processor will transition to the Active mode. When in Deep Sleep mode, assertion of the RTC asynchronous interrupt causes the processor to transition to the Full On mode, regardless of the value of the BYPASS pin. The SLEEP output is asserted in this mode, thereby enabling an external power regulator to determine when it is safe to vary the processor core's VDD.
Mode Transitions
RELAXED
SL EE P
ACT IVE
F UL L ON
The available mode transitions diagrammed in Figure 6 are accomplished either by the interrupt events described in the sections below or by programming the PLLCTL register with the appropriate values and then executing the following instruction sequence: CLI; IDLE; SSYNC; STI; // disable interrupts // source NOPs into the pipeline and assert IDLE output on SSYNC // drain the pipeline, IDLE asserts after system acknowledge // re-enable interrupts after wakeup
RESET CONF I GURAT I ON
Figure 6. Mode Transitions
This instruction sequence takes the processor to a known, idle state, with the interrupts disabled. Note that all DMA activity should be disabled during mode transitions.
Dynamic Power Management
The power consumed by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in power consumption, while reducing the voltage by 25% reduces power consumption by more than 40%. Further, these power savings are additive, in that if the clock frequency and power are both reduced the power savings are dramatic. The Dynamic Power Management feature of the ADSP21535 allows both the processor's input voltage (VDDINT) and clock frequency (fCLK) to be dynamically controlled. As explained above, the savings in power consumption can be modeled by the following equation: Power Consumption Factor=(fCCLKRED /fCCLKNOM) (VDDINTRED /VDDINTNOM)2 where * * fCCLKNOM is the nominal core clock frequency (300 MHz) fCCLKRED is the reduced core clock frequency VDDINTNOM is the nominal internal supply voltage (1.5 V) VDDINTRED is the reduced internal supply voltage
As shown in Table 4, the ADSP-21535 supports five different power domains. The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-21535 into its own power domain, separate from the PLL, RTC, PCI, and other I/O, the processor can take advantage of dynamic power management, without affecting the PLL, RTC, or other I/O devices.
Table 4. ADSP-21535 Power Domains Power Domain VDD Range
* *
All internal logic, except PLL and RTC Analog PLL internal logic RTC internal logic and crystal I/O PCI I/O All other I/O, including CLKIN input buffer
VDDINT VDDPLL VDDRTC VDDPCIEXT VDDEXT
As an example of how significant the power savings of Dynamic Power Management are, when both frequency and voltage are reduced, consider an example where the frequency is reduced from its nominal value to 50 MHz and the voltage is reduced from its nominal value to 1.2 V. At this reduced frequency and voltage, the processor consumes about 10% of the power consumed at nominal frequency and voltage. 13
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Peripheral Power Control
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The ADSP-21535 provides additional power control capability by allowing dynamic scheduling of clock inputs to each of the peripherals. This allows finer control of power by enabling or disabling clocking to each of the peripherals. Clocking to each of the peripherals listed below can be enabled or disabled by appropriately setting the peripheral's control bit in the Peripheral Clock Enable Register (IOCKREG). The Peripheral Clock Enable Register allows individual control for each of the following peripherals: * * * * * * * * * * * * PCI EBIU controller GPIO MemDMA controller SPORT 0 SPORT 1 SPI 0 SPI 1 UART 0 UART 1 Timer 0, Timer 1, Timer 2 USB CLK
CLKIN MSEL0 (PF0) MSEL1 (PF1) MSEL2 (PF2) MSEL3 (PF3) MSEL4 (PF4) MSEL5 (PF5) MSEL6 (PF6) DF (PF7)
CLKOUT
VDD
ADSP-21535
VDD
THE PULL-UP/PULLDOWN RESISTORS ON THE MSEL, DF, AND BYPASS PINS SELECT THE CORE CLOCK RATIO. HERE, THE SELECTION (6:1) AND 25MHz INPUT CLOCK PRODUCE A 150MHz CORE CLOCK.
BYPASS
RESET SOURCE
RESET
Clock Signals
Figure 7. Clock Ratio Example
The ADSP-21535 can be clocked by a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If a buffered, shaped clock is used, this external clock connects to the DSP's CLKIN pin. CLKIN input cannot be halted, changed, or operated below the specified frequency during normal operation. This clock signal should be a TTL-compatible signal. The DSP provides a user-programmable 1 x to 31 x multiplication of the input clock, to support external to internal (DSP core) clock ratios. The MSEL6-0, BYPASS, and DF pins decide the PLL multiplication factor at reset. At runtime, the multiplication factor can be controlled in software. The combination of pullup and pull-down resistors in Figure 7 sets up a core clock ratio of 6:1, which, for example, produces a 150-MHz core clock from the 25-MHz input. For other clock multiplier settings, see the ADSP-21535 Hardware Reference. The peripheral clock is supplied to the CLKOUT_SCLK0 pin. All on-chip peripherals operate at the rate set by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL pins. At run time the system clock frequency can be controlled in software by writing to the SSEL f ields in the PLL control register (PLLCTL). The
values programmed into the SSEL fields define a divide ratio between the core clock (CLKIN) and the system clock. Table 5 illustrates the system clock ratios:
Table 5. System Clock Ratios Signal Name SSEL [1:0] Divider Ratio CCLK/ SCLK Example Frequency Ratios (MHz) CCLK SCLK
00 01 10 11
2:1 2.5:1 3:1 4:1
266 275 300 300
133 110 100 75
The maximum frequency of the system clock is fSCLK. Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The reset value of the SSEL [1:0] is determined by sampling the Programmable Flag input pins (PF[9:8]) during reset. The SSEL value can be changed dynamically by writing the appropriate values to the PLL control register (PLLCTL), as described in the ADSP-21535 DSP Hardware Reference.
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Booting Modes
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The ADSP-21535 has three mechanisms (listed in Table 6) for automatically loading internal L2 memory after a reset. A fourth mode is provided to execute from external memory, bypassing the boot sequence.
Table 6. Booting Modes BMODE[2:0] Description
To augment the boot modes described above, a secondary software loader is provided that adds additional booting mechanisms. This secondary loader provides the capability to boot from 16-bit flash memory, fast flash, variable baud rate, etc.
Instruction Set Description
000 001 010 011 100 -111
Execute from 16-bit external memory (Bypass Boot ROM) Boot from 8-bit flash Boot from SPI0 serial ROM (8-bit address range) Boot from SPI0 serial ROM (16-bit address range) Reserved
The BMODE pins of the Reset Configuration Register, sampled during power on resets and software initiated resets, implement the following modes: * Execute from 16-bit external memory - Execution starts from address 0x2000000 with 16-bit packing. The boot ROM is bypassed in this mode. Boot from 8-bit external flash memory - The 8-bit flash boot routine located in boot ROM memory space is set up using asynchronous Memory Bank 4. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). Boot from SPI serial EEPROM (8-bit addressable) - The SPI0 uses PF10 output pin to select a single SPI EPROM device, submits a read command at address 0x00, and begins clocking data into the beginning of L2 memory. An 8-bit addressable SPI-compatible EPROM must be used. Boot from SPI serial EEPROM (16-bit addressable) - The SPI0 uses PF10 output pin to select a single SPI EPROM device, submits a read command at address 0x0000, and begins clocking data into the beginning of L2 memory. A 16-bit addressable SPI-compatible EPROM must be used.
The Blackfin DSP family assembly language instruction set employs an algebraic syntax that was designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the DSP core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both a user (algorithm/application code) and a supervisor (O/S kernel, device drivers, debuggers, ISRs) mode of operations, allowing multiple levels of access to core DSP resources. The assembly language, which takes advantage of the processor's unique architecture, offers the following advantages: * * Seamlessly integrated DSP/CPU features are optimized for both 8-bit and 16-bit operations. A super-pipelined multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle. All registers, I/O, and memory are mapped into a unified 4-Gbyte memory space providing a simplified programming model.
*
*
*
*
Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and kernel stack pointers. * Code density enhancements, which include intermixing of 16 and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded as 16-bits.
For each of the boot modes described above, a four-byte value is first read from the memory device. This value is used to specify a subsequent number of bytes to be read into the beginning of L2 memory space. Once each of the loads is complete, the processor jumps to the beginning of L2 space and begins execution. In addition, bit 4 of the Reset Configuration Register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L2 memory space.
Development Tools
The ADSP-21535 is supported with a complete set of software and hardware development tools, including Analog Devices' emulators and the VisualDSP++(R) development environment. The same emulator hardware that supports other Analog Devices DSPs, also fully emulates the ADSP-21535. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax, an archiver (librarian/library builder), a 15
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linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to Blackfin DSP assembly. The Blackfin DSP has architectural features that improve the efficiency of compiled C/C++ code. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * * * * * * * * View mixed C/C++ and assembly code (interleaved source and object information) Insert break-points Set conditional breakpoints on registers, memory, and stacks Trace instruction execution Perform linear or statistical profiling of program execution Fill, dump, and graphically plot the contents of memory Perform source level debugging Create custom debugger windows
resources, automating the generation of various VDK based objects, and visualizing the system state, when debugging an application that uses the VDK. Analog Devices' DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-21535 to monitor and control the target board processor during emulation. The emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin DSP family. Hardware tools include the ADSP-21535 EZ-Kit standalone evaluation/development cards. Third Party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board (Target)
The VisualDSP++ IDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all development tools, including Color Syntax Highlighting in the VisualDSP++ editor. These capabilities permit programmers to: * * Control how the development tools process inputs and generate outputs. Maintain a one-to-one correspondence with the tool's command line switches.
The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on the ADSP-21535. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target's design must include the interface between an Analog Devices' JTAG DSP and the emulation header on a custom DSP target board.
Target Board Header
The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include Threads, Critical and Unscheduled regions, Semaphores, Events, and Device flags. The VDK also supports Priority-based, Pre-emptive, Cooperative and Time -Sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system
The emulator interface to an Analog Devices' JTAG DSP is a 14-pin header, as shown in Figure 8 on page 17. The customer must supply this header on the target board in order to communicate with the emulator. The interface consists of a standard dual row 0.025" square post header, set on 0.1" 0.1" spacing, with a minimum post length of 0.235". Pin 3 is the key position used to prevent the pod from being inserted backwards. This pin must be clipped on the target board. Also, the clearance (length, width, and height) around the header must be considered. Leave a clearance of at least 0.15" and 0.10" around the length and width of the header, and reserve a height clearance to attach and detach the pod connector. As can be seen in Figure 8, there are two sets of signals on the header. There are the standard JTAG signals TMS, TCK, TDI, TDO, TRST, and EMU used for emulation
16
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PRELIMINARY TECHNICAL DATA June 2001
1 GND 3 KEY (NO PIN) 5 BTM S BTCK 9 BTRST 11 BTD I 13 GND 14 TD O 9 12 TD I 10 TRS T
0.24" 0.88"
For current information contact Analog Devices at 800-262-5643
ADSP-21535
2 EMU 4 GND 6 TMS
header. This board area should contain no components (chips, resistors, capacitors, etc.). The dimensions are referenced to the center of the 0.25" square post pin.
0.64"
7
8 TCK
Figure 10. JTAG Pod Connector Dimensions
TOP VIEW
0.10"
Figure 8. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place)
purposes (via an emulator). There are also secondary JTAG signals BTMS, BTCK, BTDI, and BTRST that are optionally used for board-level (boundary scan) testing. When the emulator is not connected to this header, place jumpers across BTMS, BTCK, BTRST, and BTDI as shown in Figure 9. This holds the JTAG signals in the correct state to allow the DSP to run free. Remove all the jumpers when connecting the emulator to the JTAG header.
0.15"
Figure 11. JTAG Pod Connector Keep-Out Area Design-for-Emulation Circuit Information
1 G ND 3 K E Y (NO P IN ) 5 BT M S 7 BT C K 9 BT R S T 9 11 B TD I
2 EMU 4 GND 6 TMS 8 T CK 10 T RS T
For details on target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)-- use site search on "EE-68". This document is updated regularly to keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21535 architecture and functionality. For detailed information on the Blackfin DSP Family core architecture and instruction set, refer to the ADSP-21535 Hardware Reference and the Blackfin DSP Family Instruction Set Reference.
12 T DI
G ND
13
14 T DO
TO P V IEW
Figure 9. JTAG Target Board Connector with No Local Boundary Scan JTAG Emulator Pod Connector
Figure 10 details the dimensions of the JTAG pod connector at the 14-pin target end. Figure 11 displays the keep-out area for a target board header. The keep-out area allows the pod connector to properly seat onto the target board REV. PrA
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17
PRELIMINARY TECHNICAL DATA ADSP-21535
PIN DESCRIPTIONS
For current information contact Analog Devices at 800-262-5643
June 2001
Unused inputs should be tied or pulled to VDDEXT or GND. ADSP-21535 pin definitions are listed in Table 7. The following pins are asynchronous: ARDY, PF[15:0], USB_CLK, NMI, TRST, RESET, PCI_CLK, XTALI, XTALO.
Table 7. Pin Descriptions Pin Type Function
The following symbols appear in the Type column of Table 7: I = Input, O = Output, T = Three-State, P = Power, and G = Ground.
ADDR DATA ABE /SDQM AMS ARDY AOE ARE AWE CLKOUT /SCLK1 SCLK0 SCKE SA10 SRAS SCAS SWE SMS TMR0 TMR1 TMR2 PF[15] /SPI1SEL[7] PF[14] /SPI0SEL[7] 18
O/T I/O/T O/T O/T I O/T O O O O O/T O/T O/T O/T O/T O/T I/O/T I/O/T I/O/T I/O/T I/O/T
External address bus. External data bus. Asynchronous memory byte enables, SDRAM data masks. Chip selects for asynchronous memories. Acknowledge signal for asynchronous memories. Memory output enable for asynchronous memories. Read enable for asynchronous memories. Write enable for asynchronous memories. SDRAM clock output pin. Same frequency and timing as SCLK0. Provided to reduce capacitance loading on SCLK0. Connect to SDRAM's CK pin. SDRAM clock output pin 0. Switches at system clock frequency. Connect to the SDRAM's CLK pin. SDRAM clock enable pin. Connect to SDRAM's CKE pin. SDRAM A10 pin. SDRAM interface uses this pin to retain control of the SDRAM device during host bus requests. Connect to SDRAM's A10 pin. SDRAM row address strobe pin. Connect to SDRAM's RAS pin. SDRAM column address select pin. Connect to SDRAM's CAS pin. SDRAM write enable pin. Connect to SDRAM's WE or W buffer pin. Memory select pin of external memory bank configured for SDRAM. Connect to SDRAM's chip select pin. Timer 0 pin. Functions as an output pin in PWMOUT mode and as an input pin in WIDTH_CNT and EXT_CLK modes. Timer 1 pin. Functions as an output pin in PWMOUT mode and as an input pin in WIDTH_CNT and EXT_CLK modes. Timer 2 pin. Functions as an output pin in PWMOUT mode and as an input pin in WIDTH_CNT and EXT_CLK modes. General purpose I/O pins. SPI output select pin. General purpose I/O pins. SPI output select pin.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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Pin Type
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ADSP-21535
Table 7. Pin Descriptions (Continued) Function
PF[13] /SPI1SEL[6] PF[12] /SPI0SEL[6] PF[11] /SPI1SEL[5] PF[10] /SPI0SEL[5] PF[9] /SPI1SEL[4] /SSEL[1] PF[8] /SPI0SEL[4] /SSEL[0] PF[7] /SPI1SEL[3] /DF PF[6] /SPI0SEL[3] /MSEL[6] PF[5] /SPI1SEL[2] /MSEL[5] PF[4] /SPI0SEL[2] /MSEL[4] PF[3] /SPI1SEL[1] /MSEL[3] PF[2] /SPI0SEL[1] /MSEL[2] PF[1] /SPISS1 /MSEL[1] PF[0] /SPISS0 /MSEL[0] RSCLK0 RFS0 DR0 REV. PrA
I/O/T I/O/T I/O/T I/O/T I/O
General purpose I/O pins. SPI output select pin. General purpose I/O pins. SPI output select pin. General purpose I/O pins. SPI output select pin. General purpose I/O pins. SPI output select pin. General purpose I/O pins. SPI output select pin. Sampled during reset to determine core clock to system clock ratio. General purpose I/O pins. SPI output select pin. Sampled during reset to determine core clock to system clock ratio. General purpose I/O pins. SPI output select pin.Sensed for configuration state during hardware reset, used to configure the PLL. DF=1 is for high frequency clock and divides the input clock by 2. DF=0 passes input clock directly to PLL phase detector. General purpose I/O pins. SPI output select pin. Sensed for configuration state during hardware reset, used to configure the PLL. Selects CK to CLKIN ratio. General purpose I/O pins. SPI output select pin. Sensed for configuration state during hardware reset, used to configure the PLL. Selects CK to CLKIN ratio. General purpose I/O pins. SPI output select pin. Sensed for configuration state during hardware reset, used to configure the PLL. Selects CK to CLKIN ratio. General purpose I/O pins. SPI output select pin. Sensed for configuration state during hardware reset, used to configure the PLL. Selects CK to CLKIN ratio. General purpose I/O pins. SPI output select pin. Sensed for configuration state during hardware reset, used to configure the PLL. Selects CK to CLKIN ratio. General purpose I/O pins. SPI slave select input pin. Sensed for configuration state during hardware reset, used to configure the PLL. Selects CK to CLKIN ratio. General purpose I/O pins. SPI slave select input pin. Sensed for configuration state during hardware reset, used to configure the PLL. Selects CK to CLKIN ratio. Receive serial clock for SPORT0. Receive frame synchronization for SPORT0. Serial data receive for SPORT0. 19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/T I/O/T I
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PRELIMINARY TECHNICAL DATA ADSP-21535
Pin Type
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June 2001
Table 7. Pin Descriptions (Continued) Function
TSCLK0 TFS0 DT0 RSCLK1 RFS1 DR1 TSCLK1 TFS1 DT1 MOSI0 MISO0 SCK0 MOSI1 MISO1 SCK1 RX0 TX0 RX1 TX1 USB_CLK XVER_DATA DPLS DMNS TXDPLS TXDMNS TXEN SUSPEND NMI
I/O/T I/O/T O I/O/T I/O/T I I/O/T I/O/T O I/O I/O I/O I/O I/O I/O I O I O I I I I O O O O I
Transmit serial clock for SPORT0. Transmit frame synchronization for SPORT0. Serial data transmit for SPORT0. Receive serial clock for SPORT1. Receive frame synchronization for SPORT1. Serial data receive for SPORT1. Transmit serial clock for SPORT1. Transmit frame synchronization for SPORT1. Serial data transmit for SPORT1. Master out slave in pin for SPI0. Supplies the output data from the master device and receives the input data to a slave device. Master in slave out pin for SPI0. Supplies the output data from the slave device and receives the input data to the master device. Clock line for SPI0. Master device output clock signal. Slave device input clock signal. Master out slave in pin for SPI1. Supplies the output data from the master device and receives the input data to a slave device. Master in slave out pin for SPI1. Supplies the output data from the slave device and receives the input data to the master device. Clock line for SPI1. Master device output clock signal. Slave device input clock signal. UART0 receive pin. UART0 transmit pin. UART1 receive pin. UART1 transmit pin. USB clock. Single ended receive data output from USB transceiver to the USBD module. Differential D+ receive data output from the USB transceiver to the UBD module. Differential D- receive data output from the USB transceiver to the USBD module. Transmitted D+ from the USBD module to the USB transceiver. Transmitted D- from the USBD module to the USB transceiver. Transmit enable from the USBD module to the USB transceiver. Suspend mode enable output from the USBD module to the USB transceiver. This signal can also be routed internally by the SoC to support low power operations. Non-maskable interrupt.
20
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Table 7. Pin Descriptions (Continued) Function
TCK TDO TDI TMS TRST RESET CLKIN1 BYPASS SLEEP BMODE[2:0] PCI_AD PCI_CBE PCI_FRAME PCI_IRDY PCI_TRDY PCI_DEVSEL PCI_STOP PCI_PERR PCI_PAR PCI_REQ PCI_SERR PCI_RST PCI_GNT PCI_IDSEL PCI_LOCK PCI_CLK
I O I I I I I I O I I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T O I/O/T I/O/T I I I I
JTAG clock. JTAG serial data out. JTAG serial data in. JTAG master slave. JTAG reset. Tie to ground if not used. When this pin is asserted to logic zero level for at least 10 CLKIN cycles, a hardware reset is initiated. TShe minimum pulse width for power-on reset is 40 sec. Clock in. Dedicated mode pin. May be permanently strapped to VDD or VSS. Bypasses the on-chip PLL. Denotes that the Blackfin DSP Core is in Deep Sleep mode. Dedicated mode pin. May be permanently strapped to VDD or VSS. Configures the boot mode that is employed following hardware reset or software reset. PCI address and data bus. PCI byte enables. PCI frame signal. Used by PCI initiators for signalling the beginning and end of a PCI transaction. PCI initiator ready signal. PCI target ready signal. PCI device select signal. Asserted by targets of PCI transactions to claim the transaction. PCI stop signal. PCI parity error signal. PCI parity signal. PCI request signal. Used for requesting the use of the PCI bus. PCI system error signal. Requires a pullup on the system board. PCI reset signal. PCI grant signal. Used for granting access to the PCI bus. PCI initialization device select signal. Individual device selects for targets of PCI configuration transactions. PCI lock signal. Used to lock a target or the entire PCI bus for use by the master that asserts the lock. PCI clock.
REV. PrA
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21
PRELIMINARY TECHNICAL DATA ADSP-21535
Pin Type
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June 2001
Table 7. Pin Descriptions (Continued) Function
PCI_INTA
I/O/T
PCI interrupt A line on PCI bus. Asserted by the ADSP-21535 as a device to signal an interrupt to the system processor. Monitored by the ADSP-21535 when acting as the system processor. PCI interrupt B line. Monitored by ADSP-21535 when acting as the system processor. PCI interrupt C line. Monitored by the ADSP-21535 when acting as the system processor. PCI interrupt D line. Monitored by the ADSP-21535 when acting as the system processor. Real-Time Clock oscillator input. Real-Time Clock oscillator output. Emulator acknowledge, open drain. Must be connected to the ADSP-21535 emulator target board connector only. PLL power supply (1.5 V nominal). Real-Time Clock power supply (3.3 V nominal). I/O (except PCI) power supply (3.3 V nominal). PCI I/O power supply (3.3 V nominal). Internal power supply (1.5 V nominal). Power supply return.
PCI_INTB PCI_INTC PCI_INTD XTALI XTALO EMU VDDPLL VDDRTC VDDEXT VDDPCIEXT VDDINT GND
I I I I O I P P P P P G
22
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ADSP-21535
ADSP-21535--SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
Parameter K Grade Parameter Min Nominal Max Unit
VDDINT VDDEXT VDDPLL VDDRTC VDDPCIEXT VIH VIL TCASE
1
Internal (Core) Supply Voltage External (I/O) Supply Voltage PLL Power Supply Voltage Real Time Clock Power Supply Voltage PCI I/O Power Supply Voltage High Level Input Voltage1, @ VDDINT = max Low Level Input Voltage1, @ VDDINT = min Case Operating Temperature
0.86 2.5 1.425 3.15 3.15 2.0 -0.3 0
1.5 3.3 1.5 3.3 3.3
1.575 3.45 1.575 3.45 3.45 VDDEXT +0.5 0.6 85
V V V V V V V C
Applies to input and bidirectional pins.
Specifications subject to change without notice
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Min Max Unit
VOH VOL IIH IIL IOZH IOZL CIN
High Level Output Voltage1 Low Level Output Voltage1 High Level Input Current2 Low Level Input Current2 Three-State Leakage Current3 Three-State Leakage Current3 Input Capacitance4, 5
@ VDDEXT = min, IOH = -0.5 mA @ VDDEXT = min, IOL = 2.0 mA @ VDDEXT = max, VIN = VDD max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = VDD max @ VDDEXT = max, VIN = 0 V fIN = 1 MHz, TCASE = 25C, VIN = 2.5 V
2.4 0.4 TBD TBD TBD TBD TBD
V V A A A A pF
1 2 3 4 5
Applies to output and bidirectional pins. Applies to input pins. Applies to three-statable pins. Applies to all signal pins. Guaranteed, but not tested.
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23
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800-262-5643 ADSP-21535 ABSOLUTE MAXIMUM RATINGS
June 2001
Parameter1
Absolute Maximum Rating
Internal (Core) Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage Output Voltage Swing Load Capacitance Core Clock Peripheral Clock (SCLK) Storage Temperature Range Lead Temperature (5 seconds)
1
-0.3 V to +1.8 V -0.3 V to +4.0 V -0.5 V to VDDEXT + 0.5 V -0.5 V to VDDEXT + 0.5 V 200 pF 300 MHz 133 MHz -65C to +150C 185C
Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Specifications subject to change without notice
ESD SENSITIVITY
CAUTION: ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21535 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS
Table 8 and Table 9 on page 25 describe the timing requirements for the ADSP-21535 clocks. Take care in selecting MSEL and SSEL ratios so as not to exceed the maximum core clock and system clock operating frequencies, as described in ABSOLUTE MAXIMUM RATINGS.
Table 8. Core and System Clock Requirements Parameter Description Min Max Unit
tCCLK1.5 tCCLK1.4 tCCLK1.3 tCCLK1.2 tCCLK1.1 tCCLK1.0 24
Core Cycle Period (VDDINT =1.5 V-5%) Core Cycle Period (VDDINT =1.4 V-5%) Core Cycle Period (VDDINT =1.3 V-5%) Core Cycle Period (VDDINT =1.2 V-5%) Core Cycle Period (VDDINT =1.1 V-5%) Core Cycle Period (VDDINT =1.0 V-5%)
3.3 TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD
ns ns ns ns ns ns REV. PrA
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PRELIMINARY TECHNICAL DATA June 2001
Parameter Description
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ADSP-21535
Max Unit
Table 8. Core and System Clock Requirements (Continued) Min
tCCLK0.9 fCCLKNN tSCLK fSCLK
Core Cycle Period (VDDINT =0.9 V-5%) Core Clock Frequency at tCCLKNN System Clock Period System Clock Frequency
TBD
TBD 1/tCCLKNN
ns Hz ns
Max. of (7.5 or tCCLKNN 2) 1/tSCLK
Hz
Table 9. Clock In Timing Requirements Parameter Description Min Max Unit
tCKIN
Clock In Period
30
100
ns
REV. PrA
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25
PRELIMINARY TECHNICAL DATA ADSP-21535
Power Dissipation
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June 2001
Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. Table 10 shows the power dissipation for
Table 10. Internal Power Dissipation Parameter Test Conditions
internal circuitry. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Table 11 lists the conditions under which the values in Table 10 are obtained.
Typical (VDDINT =1.5 V)1
Typical (VDDINT =1.0 V)1
Units
IDDHIGH IDDTYP IDDLOW IDDSYS IDDEFR IDDACTIVE IDDRELAXED IDDSLEEP IDDDEEPSLEEP
1
tCCLKMIN, 25C tCCLKMIN, 25C tCCLKMIN, 25C tCCLKMIN, 25C tCCLKMIN, 25C 25C 25C 25C 25C
TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD TBD TBD
mA mA mA mA mA mA mA mA mA
Typical IDD data is specified for nominal VDDINT and typical process parameters.Maximum IDD is within TBD% of typical values.
Table 11. Internal Power Dissipation Conditions Parameter Mode PLL CCLK SCLK Activity
IDDHIGH1 IDDTYP1 IDDLOW1 IDDSYS2 IDDEFR3 IDDACTIVE IDDRELAXED IDDSLEEP IDDDEEPSLEEP
1 2 3
Full-On Full-On Full-On Full-On Full-On Active Relaxed Sleep Deep Sleep
Enabled Enabled Enabled Enabled Enabled Enabled/Bypassed Disabled /Bypassed Disabled Disabled
Enabled Enabled Enabled Enabled Enabled Enabled Enabled Disabled Disabled
Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Disabled
TBD TBD TBD TBD Algorithm dependent
TBD instruction mix. TBD instruction mix and system DMA every cycle. Implementation of Enhanced Full Rate (EFR) GSM algorithm, instruction and data fetch from L1/L2 memories and cache.
26
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ADSP-21535
ADSP-21535 256-Lead PBGA Pinout
Table 12 lists the PBGA pinout by signal name.
Table 12. 256-Lead PBGA Pin Assignment (Alphabetically By Signal) SIGNAL PIN #
Table 12. 256-Lead PBGA Pin Assignment (Alphabetically By Signal) (Continued) SIGNAL PIN #
AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BMODE0 BMODE1 BMODE2 BYPASS CLKIN1 CLKOUT DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
ABE0 ABE1 ABE2 ABE3 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
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27
PRELIMINARY TECHNICAL DATA ADSP-21535
SIGNAL PIN #
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June 2001
Table 12. 256-Lead PBGA Pin Assignment (Alphabetically By Signal) (Continued)
Table 12. 256-Lead PBGA Pin Assignment (Alphabetically By Signal) (Continued) SIGNAL PIN #
DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DMNS DPLS DR0 DR1 DT0 DT1 EMU MISO0 MISO1 MOSI0 MOSI1 NMI PCI_AD0 PCI_AD1
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
28
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Table 12. 256-Lead PBGA Pin Assignment (Alphabetically By Signal) (Continued) SIGNAL PIN #
Table 12. 256-Lead PBGA Pin Assignment (Alphabetically By Signal) (Continued) SIGNAL PIN #
PCI_CBE0 PCI_CBE1 PCI_CBE2 PCI_CBE3 PCI_CLK PCI_DEVSEL PCI_FRAME PCI_GNT PCI_IDSEL PCI_INTA PCI_INTB PCI_INTC PCI_INTD PCI_IRDY PCI_LOCK PCI_PAR PCI_PERR PCI_REQ PCI_RST PCI_SERR PCI_STOP PCI_TRDY PF0 /SPISS0 /MSEL0 PF1 /SPISS1 /MSEL1 PF2 /SPI0SEL1 /MSEL2 PF3 /SPI1SEL1 /MSEL3 REV. PrA
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
PF4 /SPI0SEL2 /MSEL4 PF5 /SPI1SEL2 /MSEL5 PF6 /SPI0SEL3 /MSEL6 PF7 /SPI1SEL3 /DF PF8 /SPI0SEL4 /SSEL0 PF9 /SPI1SEL4 /SSEL1 PF10 /SPI0SEL5 PF11 /SPI1SEL5 PF12 /SPI0SEL6 PF13 /SPI1SEL6 PF14 /SPI0SEL7 PF15 /SPI1SEL7 RESET RFS0
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 29
TBD RFS1 RSCLK0 TBD RSCLK1 RX0 TBD RX1 SA10
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PRELIMINARY TECHNICAL DATA ADSP-21535
SIGNAL PIN #
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June 2001
Table 12. 256-Lead PBGA Pin Assignment (Alphabetically By Signal) (Continued)
Table 12. 256-Lead PBGA Pin Assignment (Alphabetically By Signal) (Continued) SIGNAL PIN #
SCAS SCK0 SCK1 SCKE SCLK0 SCLK1 SLEEP SMS0 SMS1 SMS2 SMS3 SUSPEND SWE TCK TDI TDO TFS0 TFS1 TMR0 TMR1 TMR2 TMS TRST TSCLK0 TSCLK1 TX0 TX1 TXDPLS TXDMNS TXEN
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
USB_CLK XTALI XTALO XVER_DATA
TBD TBD TBD TBD
30
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OUTLINE DIMENSIONS
Dimensions in Figure 12 are shown in millimeters.
DRAWING VIEWS AND DIMENSIONS TBD
Figure 12. 256-Lead Metric Plastic Ball Grid Array (PBGA) (B-256) ORDERING GUIDE Part Number1 Case Temperature Range Instruction Rate Operating Voltage
ADSP-21535PKCA-300
1
0C to 85C
300 MHz
0.95 V to 1.575 V internal, 3.3 V-tolerant I/O
B = Plastic Ball Grid Array (PBGA).
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
31
PRELIMINARY TECHNICAL DATA June 2001
For current information contact Analog Devices at 800-262-5643
ADSP-21535
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
32

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